A dual in-line memory module (DIMM) generally refers to a module that contains one or more Random Access Memory (RAM) or Dynamic RAM (DRAM) chips on a small circuit board outfitted with certain pins for connecting to a computer motherboard. Known configurations for a DIMM include a 240-pin connector or a 160-pin connector and may support 64/72-bit data transfer. The memory devices of performance enhanced DIMMs are generally Synchronous DRAMs (SDRAMs), the terms DRAM and SDRAM being used interchangeably here.
A continuing demand for higher memory speed and capacity has led to the development of different types of DIMMs, including Registered DIMMs (RDIMMs) and LRDIMMs. An RDIMM, exemplarily shown in FIG. 1, contains a buffer that is used to reduce the loading of the clock, address, and control signals on the memory bus. An LRDIMM, exemplarily shown in FIG. 2, contains buffers for buffering the clock/address/control signals as well as for the data signals.
Although data buffering in LRDIMMS allows higher capacity modules to be developed, it also introduces additional latency compared to RDIMMs (which does not buffer data signals) due to a mismatch between the Data Queue Strobe (DQS) and when the data actually becomes available at the buffers. This additional data buffer latency of LRDIMMs creates a major issue when integrating LRDIMMs into a computer's memory system already using RDIMMs because all the DIMMs in a system are expected to have the same latency. If one DIMM is slower (i.e., longer latency), all the DIMMs are programmed with the longer latency by the host computer system. A further complication is that the delay through the data buffer is not an integer multiple of the clock period so a simple increase in the latency does not allow interoperation. The Joint Electron Device Engineering Council (JEDEC) standards, therefore, generally does not provide guidelines for using RDIMMs and LRDIMMs together. U.S. Pat. No. 8,452,917, however, provides a solution to the latency issue and discloses LRDIMMs that are timing compatible with RDIMMs.
The data buffer latency issue is not limited to LRDIMMs and also arises in co-processors and input/output devices (hereafter, “CPIO devices”) that utilize an LRDIMM interface/front end to connect to a computer's main memory system, such as those described in the now-allowed U.S. patent application Ser. No. 13/303,048. In other words, a CPIO device that connects to the computer's main memory via an LRDIMM front end also exhibits additional latency (compared to an RDIMM) due to the data buffering and is generally not compatible with RDIMMs already being used on the main memory. Therefore, there exists a need for a system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end such that the CPIO device would be timing compatible with an RDIMM.